First PPAM Workshop on RISC-V

RISC-V PPAM2024

Co-located with PPAM 2024, this is the first edition of workshops devoted to all aspects of the RISC-V technology. with a special emphasis on high performance computing (HPC), edge computing, and AI/ML

Background

The goal of this workshop is to continue building the community of RISC-V technology, sharing the benefits of this technology with computer science specialists and domain scientists. RISC-V is an open standard Instruction Set Architecture (ISA) that enables the royalty-free development of CPUs and a common software ecosystem. Following this community-driven ISA standard, a very diverse set of CPUs suited to a range of workloads have been, and continue to be, developed. While RISC-V has already become very popular in some fields, like embedded and edge computing, it has yet to gain traction in general-purpose computing, including HPC, and AI/M. In particular, recent advances in RISC-V make it a more realistic proposition for HPC workloads than ever before. An example is vectorization extension, which provides essential performance advantages for HPC workloads but was only standardized in early 2022, so we are only now seeing mature CPUs that fully implement this extension.

By sharing the benefits of the architecture, success stories, and techniques, the first edition of this Workshop aims to popularize RISC-V among the PPAM community, bringing together specialists involved in developing RISC-V hardware/software and those looking to exploit the potential of new computer architectures in a broad spectrum of domains, including general-purpose computing, HPC, embedded and edge computing, AI/ML, etc.

This Workshop is organized in technical cooperation with Codasip company and Barcelona Supercomputing Center (BSC). In particular, a keynote talk “A RISC-V vector CPU for High-Performance Computing: architecture, platforms and tools to make it happen” by Filippo Mantovani from BSC will introduce the Workshop thematics.

Topics of interest for the Workshop include (but are not limited to):

• RISC-V hardware/software ecosystem
• RISC-V in HPC
• Tools, compilers, libraries, and techniques to support the use of RISC-V for HPC
• RISC-V in embedded and edge computing
• RISC-V in general-purpose computing
• RISC-V and AI/ML
• Novel hardware and accelerators built using RISC-V
• Porting of codes to RISC-V
• Use cases and case studies that use RISC-V
• Industry papers related to RISC-V

Paper Submission and Publication

• Papers will be refereed and accepted based on their scientific merit and relevance to the Workshop topics.
• Papers presented at the Workshop will be included in the conference proceedings and published after the conference by Springer in the LNCS series.
• Before the Workshop, abstracts of accepted papers will be posted on this site.
• Authors should submit papers (PDF files) using the online submission tool.
• Papers are not to exceed 14 pages (LNCS style).
• Alternatively, abstracts delivering original works are invited to be presented at the Workshop. They should be prepared according to the Springer LNCS format on 2 pages. Accepted abstracts will be posted on the workshop site before the conference.

Best paper award

A special award including 400 euros will be awarded to the authors of the best paper/presentation.

Important Dates

Paper due: May 7, 2024 May 17, 2024
2-page abstract due: June 7, 2024 June 11, 2024
Notification of acceptance: June 17, 2024 June 21, 2024
Workshop: September 9-10, 2024
Camera-ready: October 31, 2024

Workshop Chairs

Roman Wyrzykowski - Czestochowa University of Technology, Poland
roman(at)icis.pcz.pl
Lubomir Riha - Technical University of Ostrava, Czech Republic
lubomir.riha(at)vsb.cz

Program Committee (non-final list)

Nick Brown – EPCC, University of Edinburgh, UK
Denis Dutoit - CEA, France
Teresa Cervero - Barcelona Supercomputing Center, Spain
Paweł Gepner - Warsaw University of Technology, Poland
Daniele Gregori - E4, Italy
Andreas Herten - Forschungszentrum Juelich, Germany
Aleksandar Ilic - Technical University of Lisbon, Portugal
Filippo Mantovani - Barcelona Supercomputing Center, Spain
Manolis Marazakis - University of Crete, Greece
Norbert Meyer – Poznan Supercomputing and Networking Center, Poland
Tadej Murovic - Codasip, Czech Republic
Tomasz Olas - Czestochowa University of Technology, Poland
Olivier Perks - Rivos Inc., USA
Estela Suarez - Forschungszentrum Juelich, Germany
Lilia Zaourar - CEA, France

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